Fractional-N phase-locked loops (PLLs) can be used for synthesizing frequencies at a non-integer scalar frequency of an input reference signal. Phase coherent means that the phase relationship between the input reference signal and the output signal is deterministic. However, it has been found in existing fractional-N PLLs that when the PLL tunes away from one frequency to another frequency and returns to the original frequency, the relationship between the phase of the output signal and the phase of the input reference signal is not phase coherent. In other words, when changing from a frequency A to a frequency B and then back to the frequency A signal, the phase of the frequency A signal is not necessarily matched to that of the previously generated frequency A signal. Further, with existing fractional-N PLLs, the phase difference between an originally-generated frequency A signal and a subsequently-generated frequency A signal may be significantly more than a rounding error of a few degrees. In fact, the phase can be any phase, 0 to 360 degrees, based on the fractional part of the divide word. If the fraction is 0.25, there are 4 possible phases. If the fraction is 0.1, there are 10 possible phases, etc. In fractional-N PLL architectures, a delta-sigma modulator (DSM) can be used to generate a sequence that enables fractional reference frequency tuning of a voltage-controlled or digitally-controlled oscillator.
The DSM reduces the magnitude of fractional spurs near the PLL carrier in comparison to single accumulator fractional-N PLLs. For phase coherency, the PLL should return to the same phase relative to the PLL reference. However, DSMs may have hidden states that cause the PLL to return to a random phase relative to the reference when tuning away from a frequency and back again. This occurrence may break phase coherency. Phase coherency is particularly important when considering multiple instances of the frequency synthesizers in a given system. In a conventional fractional-N PLL, the DSM (sometime designated as ΣΔ modulator) is clocked off the divided waveform. The modulus control to the loop divider should only change when a divide cycle is complete. To this end, the edge of the divided waveform generally denotes a time when the loop divider has finished a divide cycle. Because there is a fixed time relationship between the finishing of a divide and the update of the divide word, phase coherence is maintained. Difficulties can arise, however, when the DSM is not clocked off the divided waveform.